High-Level Power Analysis and Optimization

1. Introduction.- 1.1 Low power design.- 1.2 Design abstraction and levels of the design hierarchy.- 1.3 Benefits of high-level power analysis and optimization.- 1.4 Book overview.- 2. Background.- 2.1 Sources of power consumption.- 2.2 Methods for reducing power and energy consumption.- 2.3 High-level design techniques.- 2.4 High-level synthesis application domains.- 3. Architecture-Level Power Estimation.- 3.1 Analytical power models.- 3.2 Characterization based activity and power macromodels.- 3.3 Power and switching activity estimation techniques for control logic.- 3.4 Conclusions.- 4. Power Management.- 4.1 Clock-based power management: Gated and multiple clocks.- 4.2 Pre-computation.- 4.3 Scheduling to enable power management.- 4.4 Operand isolation.- 4.5 Power management through constrained register sharing.- 4.6 Controller-based power management.- 4.7 Conclusions.- 5. High-Level Synthesis For Low Power.- 5.1 Behavioral transformations.- 5.2 Module selection.- 5.3 Resource sharing.- 5.4 Scheduling.- 5.5 Supply voltage vs. switched capacitance trade-offs.- 5.6 Optimizing memory power consumption during high-level synthesis.- 5.7 Reducing glitching power consumption during high-level design.- 5.8 Conclusions.- 6. Conclusions And Future Work.- References.