High-Speed Clock Network Design

Preface.

1: Introduction.
1.1. Clock frequency and power consumption.
1.2. Sources of clock skew and clock jitter.
1.3. On-die variations and clock skew impacts.
1.4. Clock buffer circuit design.
1.5. Power supply and reliability issues.
1.6. Design complexity of clock distribution.
1.7. Summary.

2: Overview to Timing Constraints.
2.1. Propagation delay and transition time.
2.2. Setup time constraint.
2.3. Hold time constraint.
2.4. Recovery time and pulse width.
2.5. Time borrowing.
2.6. One example: fixing holding time violations.
2.7. Delay slack graph for timing constraints.
2.8. Summary.

3: Sequential Clocked Elements.
3.1. Latch clocking.
3.2. Flip-flop clocking.
3.3. Power reduction.
3.4. Summary.

4: Design Methodology for Domino Circuits.
4.1. Domino circuit types.
4.2. Clock distribution for domino circuits.
4.3. Design optimization in domino circuits.
4.4. Low Vt devices for domino circuits.
4.5. Summary.

5: Clock Generation and De-skewing.
5.1. On-chip clock generation.
5.2. Characterization of clock generator.
5.3. Layout guidelines.
5.4. De-skewing circuits.
5.5. Clock shrinking technique for silicon debug.
5.6. Summary.

6: Microprocessor Clock Distribution Examples.
6.1. Intel IA-
64.
6.2. Intel Pentium IV.
6.3. Intel Pentium III.
6.4. DEC Alpha.
6.5. IBM Power PC.
6.6. Summary.

7: Clock Network Simulation Methods.
7.1. RC extraction.
7.2. Full-chip clock tree racing.
7.3. Click tree simulation and report files.
7.4. IR drop effects.
7.5. Summary.

8: Low-Voltage Swing Clock Distribution.
8.1. 1/2Vdd swing local clock distribution.
8.2. Low voltage swing global clock distribution.
8.3. Summary.

9: Routing Clock on Package.
9.1. Scheme overview.
9.2. ESD design.
9.3. Transmission line noise on package.
9.4. Microprocessor experimental results.
9.5. Summary.

10: Balanced Clock Routing Algorithms.
10.1. Planar equal path length clock routing.
10.2. Geometrical