Pro TBB

Part I.- Chapter 1: Jumping Right In - "Hello, TBB!".- Chapter 2: Generic Parallel Algorithms.- Chapter 3: Flow Graphs.- Chapter 4: TBB and the C++ Parallel Standard Template Library.- Chapter 5: Synchronization: why and how to avoid it.- Chapter 6: Data Structures for Concurrency.- Chapter 7: Scalable Memory Allocation.- Chapter 8: Mapping Parallel Patterns to TBB.- Part II.- Chapter 9: The Pillars of Composability.- Chapter 10: Using tasks to create your own algorithms.- Chapter 11: Controlling the Number of Threads Used for Execution.- Chapter 12: Using Work Isolation for Correctness and Performance.- Chapter 13: Creating Thread-to-core and Task-to-thread Affinity.- Chapter 14: Using Task Priorities.- Chapter 15: Cancellation and Exception Handling.- Chapter 16: Tuning TBB Algorithms: Granularity, Locality, Parallelism and Determinism.- Chapter 17: Flow Graphs: Beyond the Basics.- Chapter 18: Beef up Flow Graphs with Async Nodes.- Chapter 19: Flow Graphs on steroids: OpenCL Nodes.- Chapter 20: TBB on NUMA architectures.- Appendix A: History and Inspiration.- Appendix B: TBB Précis.- Glossary.  

Michael Voss is a Principal Engineer in the Intel Architecture, Graphics and Software Group at Intel. He has been a member of the TBB development team since before the 1.0 release in 2006 and was the initial architect of the TBB flow graph API. He is also one of the lead developers of Flow Graph Analyzer, a graphical tool for analyzing data flow applications targeted at both homogeneous and heterogeneous platforms. He has co-authored over 40 published papers and articles on topics related to parallel programming and frequently consults with customers across a wide range of domains to help them effectively use the threading libraries provided by Intel. Prior to joining Intel in 2006, he was an Assistant Professor in the Edward S. Rogers Department of Electrical and Computer Engineering at the University of Toronto. He received his Ph.D. from the School of Electrical and Computer Engineering at Purdue University in 2001.
Rafael Asenjo, Professor of Computer Architecture at the University of Malaga, Spain, obtained a PhD in Telecommunication Engineering in 1997 and was an Associate Professor at the Computer Architecture Department from 2001 to 2017. He was a Visiting Scholar at the University of Illinois in Urbana-Champaign (UIUC) in 1996 and 1997 and Visiting Research Associate in the same University in 1998. He was also a Research Visitor at IBM T.J. Watson in 2008 and at Cray Inc. in 2011. He has been using TBB since 2008 and over the last five years, he has focused on productively exploiting heterogeneous chips leveraging TBB as the orchestrating framework. In 2013 and 2014 he visited UIUC to work on CPU+GPU chips. In 2015 and 2016 he also started to research into CPU+FPGA chips while visiting U. of Bristol. He served as General Chair for ACM PPoPP'16 and as an Organization Committee member as well as a Program Committee member for several HPC related conferences (PPoPP, SC, PACT, IPDPS, HPCA, EuroPar, and SBAC-PAD). His research interests include

"Pro TBB ... is an invaluable book ... . The book provides comprehensive coverage of a full-fledged model of parallelism. Besides the TBB constructs, various mechanisms that address issues of exception handling, task partitioning, concurrent data structures, mutual exclusion, granularity, and task-thread affinity are elaborated and evaluated in great detail. The first part of the book is a light introduction to TBB, and the second part provides an in-depth presentation with examples and a performance analysis of TBB constructs." (B. Belkhouche, Computing Reviews, July 29, 2021)